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Address decoders are implemented through programmable read only memory (PROM) as: 1. Versatile, since the selection of devices is determined by the programming. 2. Memory blocks can be of different sizes 3. Lookup tables can become very large for more than 8 address lines.

There are two type of address decoders: Full Address Decoder (FAD): All address buses of processor must be connected. Partial Address Decoder (PAD): Only a few selected address buses are connected. PAD using combinational circuit and PAD using MSI chip.

The simplest method of constructing decoding circuitry is the use of a NAND gate. The output of a NAND gate is active low, and the CS pin is also active low, which makes them a perfect match. In cases where the CS input is active high, an AND gate must be used. Using a combination of NAND gates and inverters, one can decode any address range.

The most common address decoder using MSI technology are: 74139 (2-4 decoder), 74138 (3-8 decoder) and 74154 (4-16 decoder).

In connecting a memory chip to the CPU, note the following points: 1. The data bus of the CPU is connected directly to the data pins of the memory chip. 2. Control signals RD (read) and WR (memory write) from the CPU are connected tothe OE (output enable) and WE (write enable) pins of the memory chip, respectively. 3. In the case of the address bus

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